Scan-based testing has been widely used in digital circuits as a design-for-test (DFT) technique. Scan elements and related clocking circuitry take up about 30% of silicon area of an IC chip. It is estimated that 50% of chip failures are found to be caused by scan chain defects. Diagnosing scan chain faults is thus important to guide silicon debug, physical failure analysis (PFA), and yield learning process.
Some of the diagnosis techniques are based on algorithmic diagnosis processes. To determine candidates of faulty scan chains/cells (also referred to as suspected faulty scan chains/cells or faulty scan chain/cell suspects), observed failing and passing test responses are analyzed with software-based tools. These techniques are relatively straightforward for circuits that do not utilize compression techniques for testing. For circuits having embedded compression hardware, however, accurate fault diagnosis presents a formidable challenge.
Compression techniques have been widely adopted to handle large volumes of test data and to increase test speed. The implementation of such techniques typically includes inserting some hardware block (which is termed generally a “compactor” for purposes of this disclosure) along the scan path on the output side of a scan-based or partially-scan-based circuit-under-test. The compactor compresses test response data captured by scan chains in the circuit-under-test and outputs a data stream of compacted test responses through a small number of scan-output channels for analysis.
One main category of compactors is based on spatial compression. Examples of spatial compactors include the “EDT compactor” described in Rajski J., et al., “Embedded Deterministic Test for Low-Cost Manufacturing,” Proc. ITC 2002, pp. 301-310 (2002), the “X-compactor” described in Mitra S., et al., “X-Compact: An Efficient Response Compaction Technique for Test Cost Reduction,” Proc. ITC 2002, pp. 311-320 (2002), and the “I-compactor” described in Patel, J. H., et al., “Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns”, VTS, pp. 107-112 (2003). Some of these compactors or their variants have been adopted by commercial tools.
To identify faulty scan chains coupled to a compactor, a masking technique may be employed, as disclosed in the family of U.S. Pat. No. 7,729,884, “Compactor independent direct diagnosis of test hardware.” FIG. 2 illustrates an example of using a masking technique for chain diagnosis involving a compactor. In the figure, an XOR gate 250 represents a simplified compactor. To observe data unloaded from a scan chain 210, a masking pattern stored in a mask register 260 sets “0” at the second output of a decoder 230. The data shifted out of a scan chain 220 are blocked by an AND gate 280 from combining with those out of the scan chain 210. If the scan chain 210 is a faulty chain with a stuck-at-1 fault, all “1”s will be observed at the output channel of the compactor. Subsequently, a chain diagnosis technique for non-compression testing can be applied.
While straightforward, this masking approach requires extra hardware for masking and associated masking patterns. As seen in the example illustrated in FIG. 2, the extra hardware includes the decoder 230, the mask register 260, and the two AND gates 270-280. It is advantageous to search for techniques that do not increase hardware footprints for testing.